1. Field of the Invention
The present invention relates to a compound semiconductor switch circuit device. In particular, the present invention relates to a compound semiconductor switch circuit device in which insertion loss is reduced.
2. Description of the Related Art
In mobile communication instruments such as cellular phones, microwaves in the GHz band are often used. In many cases, switch elements for switching among such high-frequency signals are used in antenna switch circuits and transmit-receive switch circuits. Since such switch elements deal with high frequencies, field-effect transistors (hereinafter referred to as “FETs”) constructed using gallium arsenide (GaAs) are often used as the switch elements. Along with this, monolithic microwave integrated circuits (MMICs) are being developed into which the switch circuits themselves are integrated.
Further, as illustrated in FIGS. 13 and 14, a technology is known in which protecting elements 200 having n+/i/n+ structures are connected between two terminals of an element to be protected, in order to greatly improve electrostatic breakdown voltage in a compound semiconductor device.
FIG. 13 is a circuit diagram illustrating a compound semiconductor switch circuit device called a single-pole double-throw (SPDT) switch constructed using GaAs FETs.
The sources (or drains) of FET1 as a first FET and FET2 as a second FET are connected to a common input terminal IN. The gates of FET1 and FET2 are connected to first and second control terminals Ctl1 and Ctl2 through control resistors R1 and R2, respectively. The drains (or sources) of the FETs are connected to first and second output terminals OUT1 and OUT2, respectively.
FIG. 14 illustrates one example of a compound semiconductor chip into which the switch circuit device of FIG. 13 is integrated.
Pads I, O1, O2, C1, and C2 which respectively serve as the common input terminal IN, the first and second output terminals OUT1 and OUT2, and the first and second control terminals Ctl1 and Ctl2 are provided around FET1 and FET2 in a peripheral portion of a substrate. Source and drain electrodes 315 and 316 of FET1 are placed in a state in which comb-teeth-like portions are engaged. The gate electrode 317 thereof is placed between the source and drain electrodes 315 and 316.
A peripheral impurity region 350 for improving isolation is provided around each pad 330. Further, the control resistors R1 and R2, which are impurity regions, are placed near the common input terminal pad I and the first and second output terminal pads O1 and O2. Thus, protecting elements 200 having n+/i/n+ structures are connected between the common input terminal IN and the first control terminal Ctl1 (or second control terminal Ctl2) and between the first output terminal OUT1 (or second output terminal OUT2) and the first control terminal Ctl1 (or second control terminal Ctl2), and static electricity is discharged. This technology is described for instance in Japanese Patent Application Publication No. 2004-103786.
It is effective that electrostatic energy applied between the common input terminal IN and the first control terminal Ctl1 (or second control terminal Ctl2) is discharged immediately near the pads which serve as these terminals. Accordingly, it is desirable that protecting elements are connected in the vicinities of the pads.
The peripheral impurity regions 350 for improving isolation are respectively placed around the pads. Further, the first and second control terminal pads C1 and C2 are respectively connected to the gate electrodes of FET1 and FET2 using connecting paths. Each of these connecting paths is a resistor (control resistor) R1 (or R2) having a predetermined resistance value, which is constituted by an impurity region. The connecting paths prevent high-frequency signals from leaking from the gate electrodes to the control terminals, which are at GND potential for high frequencies.
Accordingly, the control resistor R1 (or R2) is placed along and near the common input terminal pad I to be spaced therefrom by a distance of 4 μm. Thus, a protecting element 200 including the control resistor R1 (or R2), the peripheral impurity region 350, and an insulating region (GaAs substrate) therebetween is connected between the common input terminal IN and the first control terminal Ctl1 (or second control terminal Ctl2). Accordingly, the above-described pattern can greatly improve electrostatic breakdown voltage.
However, there is the problem that insertion loss increases if the control resistor R1 (or R2) is brought close to the common input terminal pad I immediately near the first control terminal pad Ctl1 (or second control terminal pad Ctl2).
A high-frequency analog signal, which is an input signal, transmits through the common input terminal IN. However, since the control resistor R1 (or R2) is placed near the common input terminal pad I to be spaced therefrom by a distance of 4 μm, part of the input signal leaks to the control resistor R1 (or R2) in some cases. The first control terminal Ctl1 (or second control terminal Ctl2) to which the control resistor R1 (or R2) is connected is at GND potential for high frequencies. Accordingly, the high-frequency analog signal leaks to the first control terminal Ctl1 (or second control terminal Ctl2) through the control resistor R1 (or R2).
Essentially, the insertion loss of the switch MMIC is determined by only parasitic components in the FETs, i.e., parasitic resistive components, parasitic capacitive components, and parasitic inductive components of the FETs. Thus, the performance of the FETs directly determines the insertion loss of the switch MMIC.
However, in the pattern of FIG. 14, since the leakage of a high-frequency signal occurs because of a defect cause on a pattern layout other than the FETs, insertion loss increases accordingly. That is, the insertion loss of the switch MMIC having the pattern of FIG. 14 is 0.15 dB larger than that for the case where insertion loss is determined by only parasitic components of FETs. Thus, the deterioration of insertion loss has been a problem.